Test equipment is typically used to determine whether a device under test ("DUT") follows a set of timing specifications. Accordingly, timing accuracy plays a vital role in the design of test equipment because a discrepancy in the timing accuracy can result in an incorrect classification of a DUT. For example, in some testing environments, provided a DUT follows a set of predetermined timing specifications, the DUT is categorized as a valid device for sale. Typically to pass as a valid device, each pin of a given DUT must satisfy timing requirements such as valid time, hold time, and setup time. These timing requirements, however, are susceptible to both electrical noise and transmission noise.
To counteract the effect of noise, conventional testers add a guardband to timing measurements. The timing guardband ensures that pin timings are not a product of noise. One disadvantage of adding a guardband results in the testing equipment failing valid devices. In particular, the guardband makes the timing specification more stringent, thus DUTs that pass the timing specification but fail the guardband requirements are classified as failing devices.
FIG. 1 illustrates a prior art testing system. In particular, test system 100 comprises tester 120 coupled to a device under test (105). Tester 120 includes two logic paths, denoted as channel 125 and channel 130, that generate test vectors along signal lines 140 and 150. Typically, each logic path is coupled to a unique driver. For example, as illustrated in FIG. 1, channel 125 is coupled to driver 126 and channel 130 is coupled to driver 131.
Using drivers 126 and 131, tester 120 places different voltages on DUT 105's input pads (110 and 115). For example, DUT 105 realizes a logic "1" value as 5 volts and a logic "0" value as 0 volts. Accordingly, to drive pad 110 to a logic "1" value, driver 126 must drive 5 volts on line 140. Similarly, to drive pad 115 to a logic "0" value, driver 131 must drive 0 volts on line 150. Thus, by varying the voltage values on line 140 and line 150, tester 120 is able to exercise the inputs of DUT 105 and determine whether DUT 105's inputs satisfy a set of timing specifications. Provided each of DUT 105's inputs are coupled to independent logic circuits, tester 120 allows for an accurate measurement of DUT 105's input timings.
In high speed applications, however, to counteract the effects of noise some devices include inputs coupled to differential circuits. Typically a pair of differential inputs are coupled to a differential amplifier and the differential inputs are used to realize the logic value of a given input. Differential inputs are used in high speed applications because a voltage measurement based on the difference in the value between a pair of differential inputs is less susceptible to electrical noise and transmission line reflections. Conventional testers, however, have numerous disadvantages when used in conjunction with the differential inputs of a DUT.
One disadvantage of using conventional tester with differential inputs results in matching the rise time and fall time of a tester generated differential input. In particular, as the testing frequency increases, jitter in the tester's drivers results in a misalignment of the tester generated differential inputs. Typically, jitter in a tester's driver is created by power spikes, cross-talk between different components of the driver, and different delay paths between the differential signals. Additionally, possible timing errors between the tester's independent channels may add to the misalignment of the tester generated differential input. The misalignment between rise and fall times of the tester generated differential input results in an inaccurate characterization of the DUT.
FIG. 1 also illustrates the misalignment between rise and fall times when tester 120 is used to generate a differential input. The horizontal axis of timing chart 190 shows time ("t"). The vertical axis of timing chart 190 shows the voltage level on pads 110 and 115. In particular, signal 160 denotes the voltage level on pad 115 and signal 170 denotes the voltage level on pad 110. Provided, tester 120 operates at a low frequency without noise on tester 120 outputs, signals 160 and 170 intersect at time 10. Accordingly, DUT 105's inputs are exercised at time 10.
As previously described, however, during the testing of high speed devices tester 120 is susceptible to noise. For example, in high frequency applications jitter and/or channel timing errors results in the shift of signal 170. Signal 180 illustrates a possible shift of signal 170. Accordingly, the intersection between the high-to-low transition of signal 160 and the low-to-high transition of signal 180 occurs at time 12. Thus, DUT 105's inputs are exercised at time 12 resulting in the inaccurate testing of DUT 105. In particular, a test system 100 that expects an output transition based on an input transition at time 10 will incorrectly determine that DUT 105 does not follow timing specifications. To counteract the rise and fall time misalignments in tester generated differential signal some prior art system add a guardband to the timing requirement. As previously described, however, adding a guardband makes the timing specification more stringent, thus leading to the incorrect classification of some DUTs.